Field of the Invention
This invention relates to semiconductor chip package design for high speed SerDes signals which achieves low substrate differential impedance discontinuity from BGA balls to C4 bumps. It also provides an optimization method for calculating parameters of such a package.
Description of the Related Art and Background
To meet the increasing demand for high speed chip-to-chip communication, today's advanced semiconductor chips require high speed SerDes (Serializer/Deserializer) interconnections. The leading edge SerDes data rate has increased from 10 Gb/s to 25-28 Gb/s. SerDes differential impedance discontinuity in a package substrate is a key parameter in determining SerDes eye diagram quality. A high impedance mismatch along the path from ball grid array (BGA) ball to C4 bump will create large signal reflections and degrade signal quality and as a result, reduce eye opening. Unfortunately, in a semiconductor package the impedance mismatch is a natural outcome because of different structures: BGA ball, via, PTH (plated-through-hole), trace, and C4 bump. They are required to accomplish electrical interconnection in a robust mechanical enclosure. Usually each structure has a different characteristic impedance. Connecting them together will naturally create impedance mismatch. If the impedance discontinuity of a SerDes signal could be reduced, the eye diagram at the receiver end could be opened wider. A widely opened eye diagram allows two SerDes chips to be placed at a greater distance away from each other on a PCB. If a cable is used in the communication between two SerDes chips placed on two different PCBs, then a longer cable could be deployed, benefiting from an improved eye diagram. A good eye diagram also reduces the bit error rate in data transmission.
The increase in substrate impedance variation at 25 Gb/s and beyond has become a major concern in SerDes signal communication. At 10 Gb/s data rate, the rise time is roughly 20 ps. It is relatively easy to control the package substrate differential impedance to be less than ±10% of its designed value. A commonly used method is to enlarge the antipad size for BGA ball pad, via pad, and PTH pad. An antipad is a clear area around a feature or landing pad where the metal ground plane is removed. However, at >25 Gb/s data rate, these simple methods are no longer effective to meet the desired requirement of less than ±10% differential impedance variation from BGA ball to C4 bump.
FIG. 1 depicts a substrate cross section of a flip-chip BGA package. SerDes signals from silicon die bumps (C4 bumps) 11 are transmitted to BGA balls 20 through front-side vias 14, differential traces 13, PTHs 16, and back-side vias 18. For a good package design that has a differential impedance discontinuity of less than ±10% at 10 Gb/s data rate, the impedance variation for the same package design should be close to 30% when running signals at 25 Gb/s. Here the fast edge rate of signal switching due to reduced rise time makes the signal impedance more sensitive to package discontinuity.
Package horizontal interconnection for a SerDes differential signal is achieved by routing two traces in parallel in a metal layer. It is well known that by properly controlling the trace width and spacing of the two traces, it is possible to obtain desired differential trace impedance of about 100 Ohms. However, for a vertical interconnection, maintaining a 100-Ohm differential impedance from BGA ball to C4 bump (including vias and PTHs) is difficult because their diameters and heights, as well as spacing, are different from each other. This makes their differential impedance different too. FIG. 2 is a TDR (Time Domain Reflectometry) plot showing a SerDes signal differential impedance discontinuity inside a package and enlargement due to reduced rise time. Different package structures, BGA ball, via, PTH, trace and C4 bump, have different impedances. The TDR plot shows the substrate impedance discontinuity from BGA ball to via/PTH and then from trace to C4 bump. At 10 Gb/s data rate (dash-dotted line), the rise time is about 20 ps and the differential impedance mismatch can be controlled within 10%. However, for the same design at 25 Gb/s data rate (solid line), the rise time is about 8 ps and the differential impedance mismatch could be close to 30% and range from 70 Ohms to 130 Ohms. In other words, the impedance mismatch increases with the increase of data rate. Because of the large impedance mismatch and the vast amount of signal reflection, vertical differential impedance optimization to lower the variation becomes difficult. In addition, each vertical interconnection, BGA ball, via, and PTH has a slightly larger landing pad (landing pads are shown in FIG. 1 as bump landing pad 12, via landing pad 15, PTH landing pad 17, and ball landing pad 19). Its function is to ensure the manufacture tolerance of the drill alignment for via. The PTH in substrate manufacture is considered and the BGA ball attachment tolerance in assembly process is taken into account. All these tolerances make the adjacent interconnections solid. But the various landing pads from layer to layer make the impedance even more difficult to control. Furthermore, there are horizontal metal planes from each layer surrounding the vertical interconnections. Their impact on the differential impedance of a vertical SerDes signal cannot be neglected. Finally, the transition from vertical interconnection to horizontal interconnection imposes a challenge to package design because matching the impedance at the transition point is not easy.